Memory device for use in high-speed block pipelined...

Details Memory device for use in high-speed block pipelined... Memory device for use in high-speed block pipelined...

2006-05-30

2006-05-30

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000

Reexamination Certificate

active

07055087

ABSTRACT:
A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

REFERENCES:
patent: 4725987 (1988-02-01), Cates
patent: 5633686 (1997-05-01), Boden
patent: 6041368 (2000-03-01), Nakatsuji et al.

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