Memory device for retaining data during power-down mode and...

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

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C365S189090, C365S207000

Reexamination Certificate

active

07492654

ABSTRACT:
A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense amplifier in response to the internal control signal.

REFERENCES:
patent: 5875143 (1999-02-01), Ben-Zvi
patent: 5903507 (1999-05-01), Arimoto
patent: 6097658 (2000-08-01), Satoh et al.
patent: 6167484 (2000-12-01), Boyer et al.
patent: 6928016 (2005-08-01), Nam et al.
patent: 7110294 (2006-09-01), Kawai
patent: 7193896 (2007-03-01), Shiga
patent: 2002-260383 (2002-09-01), None
patent: 2005-038502 (2005-02-01), None
patent: 2001-0008981 (2001-02-01), None
patent: 428301 (2001-04-01), None
patent: 446945 (2001-07-01), None
English language abstract of Korean Publication No. 2001-0008981.
English language abstract of Japanese Publication No. 2002-260383.
English language abstract of Japanese Publication No. 2005-038502.

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