Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-06
2008-10-28
Chung, Phun M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000
Reexamination Certificate
active
07444566
ABSTRACT:
A method and apparatus is presented for extracting sparse failure information from an error data image of a memory device by scanning the error data image in only two passes. During a first scan pass, the error data image is scanned for failures in a first set of memory cell groups organized along a first dimension, keeping track of failures seen in each of the respective memory cell groups in the first set, and keeping track of and designating as a must-repair memory cell group any memory cell group whose respective number of failures equals or exceeds a first maximum failure threshold. During a second scan pass, the error data image is scanned for failures in a second set of memory cell groups organized along a second dimension, keeping track of failures seen in each of the respective memory cell groups in the second set, and keeping track of and designating as a must-repair memory cell group any memory cell group whose respective number of failures equals or exceeds a second maximum failure threshold; and generating tag images containing only sparse failure information.
REFERENCES:
patent: 6667918 (2003-12-01), Leader et al.
patent: 7055074 (2006-05-01), Hughes et al.
patent: 7339844 (2008-03-01), Krech et al.
Chung Phun M
Holland & Hart LLP
Verigy (Singapore Pte. Ltd.
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