Memory device employing open bit line architecture for...

Details Memory device employing open bit line architecture for... Memory device employing open bit line architecture for...

2006-04-11

2006-04-11

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S190000

Reexamination Certificate

active

07027339

ABSTRACT:
A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

REFERENCES:
patent: 5523975 (1996-06-01), Reddy
patent: 5835425 (1998-11-01), Berger
patent: 6571352 (2003-05-01), Blodgett
patent: 010093664 (2001-10-01), None
patent: 040008024 (2004-01-01), None

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