Memory device employing multilevel storage circuits

Details Memory device employing multilevel storage circuits Memory device employing multilevel storage circuits

1985-08-28

1988-09-13

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365220, 365230, 365238, 364200, G11C 700, G11C 800, G06F 1500

Patent

active

047714042

ABSTRACT:
A memory device which employs multilevel memory cells has a basic arrangement in which a write device writes multilevel information corresponding to binary data of plural bits in the memory cells and a readout device outputs binary data of plural bits representing the multilevel information read out of the memory cells. The memory device includes a multilevel detector for detecting the information of the memory cells at one time and reference level generator for generating reference levels therefor, thereby permitting the reduction of the bit area of each memory cell and increased speed during the operation of the memory device.

REFERENCES:
patent: 4134150 (1979-01-01), Shiga
patent: 4493059 (1985-01-01), Isogai
patent: 4661929 (1987-04-01), Aoki et al.

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