Memory device communicating with a host at different speeds...

Details Memory device communicating with a host at different speeds... Memory device communicating with a host at different speeds...

2009-08-10

2011-10-18

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S008000, C710S009000, C710S010000, C710S038000, C710S316000

Reexamination Certificate

active

08041861

ABSTRACT:
A memory device includes a high speed port, a low speed port, at least a first memory bank, a first register, and a multiplexer. The at least first memory bank is shared by the high speed port and the low speed port. The first register store information that indicates which one of the ports has permission to access the first memory bank. The multiplexer connects one of the high speed port or the low speed port to the first memory bank, in response to the information stored in the first register.

REFERENCES:
patent: 6052739 (2000-04-01), Bopardikar et al.
patent: 6119196 (2000-09-01), Muller et al.
patent: 6199150 (2001-03-01), Yoshikawa
patent: 6707818 (2004-03-01), Kadambi et al.
patent: 7151893 (2006-12-01), Hayashi et al.
patent: 2006/0187837 (2006-08-01), Warren et al.
patent: 2006/0282567 (2006-12-01), Bhesania et al.

Affiliated with

Also associated with

Rating

Memory device communicating with a host at different speeds... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device communicating with a host at different speeds..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device communicating with a host at different speeds... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4283300