Memory device capable of refreshing data using buffer and...

Details Memory device capable of refreshing data using buffer and... Memory device capable of refreshing data using buffer and...

2007-08-28

2007-08-28

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189050, C365S195000

Reexamination Certificate

active

11256879

ABSTRACT:
An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes a buffer unit configured to generate a refresh indication signal to a first one of the plurality of banks of memory and to receive buffer write data addressed to the first one of the plurality of banks of memory in response to receiving a refresh-access interrupt signal from the one of the plurality of banks of memory. The plurality of banks of memory and the buffer unit may be separate DRAM chips.

REFERENCES:
patent: 6449685 (2002-09-01), Leung
patent: 6584033 (2003-06-01), Ayukawa et al.
patent: 6707743 (2004-03-01), Leung et al.
patent: 6757784 (2004-06-01), Lu et al.
patent: 1020020057307 (2002-07-01), None

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