Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2005-05-05
2008-05-20
Trimmings, John P. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S025000, C714S030000, C714S042000, C714S048000, C714S718000, C714S719000, C714S720000, C714S733000, C714S735000, C714S818000, C714S819000, C714S824000, C365S201000, C365S189050, C365S189011
Reexamination Certificate
active
07376889
ABSTRACT:
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.
REFERENCES:
patent: 6182254 (2001-01-01), Bae
patent: 6311299 (2001-10-01), Bunker
patent: 7013413 (2006-03-01), Kim et al.
patent: 7047461 (2006-05-01), Yamazaki et al.
patent: 7228477 (2007-06-01), Thalmann
patent: 20000066545 (2000-11-01), None
patent: 20010004204 (2001-01-01), None
Cha Jae Hoon
Lee Geun Il
Ladas & Parry LLP
Trimmings John P.
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