Memory device and system with leakage blocking circuitry

Details Memory device and system with leakage blocking circuitry Memory device and system with leakage blocking circuitry

1997-08-05

1999-06-22

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518909, 326 27, 326 83, G11C 700

Patent

active

059148985

ABSTRACT:
A method and apparatus for applying a blocking potential for gating inputs of pull-up and pull-down devices of an output driver is described. The blocking potential is applied to either or both of a pull-up or pull-down transistor for reducing leakage current. In particular, a circuit having a voltage generator for producing the blocking polarity potential is connected to a voltage translator. A control signal is provided to the voltage translator for accessing the output driver. During accessing of the output driver, the blocking polarity potential is isolated from gating inputs of the pull-up and pull-down devices of the output driver. In a memory device employing the output driver, the blocking polarity potential is applied when the memory is in a state which does not activate the output driver. The blocking polarity is provided by a voltage divider using a substrate bias potential. A feedback path is employed to follow voltage applied to an output pad through substrate bias voltage.

REFERENCES:
patent: 5274276 (1993-12-01), Casper et al.
patent: 5369317 (1994-11-01), Casper et al.
patent: 5513140 (1996-04-01), Merritt
patent: 5559452 (1996-09-01), Saito
patent: 5587671 (1996-12-01), Zagar et al.
patent: 5602783 (1997-02-01), Ong

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