Memory device and serial-parallel data transform circuit

Details Memory device and serial-parallel data transform circuit Memory device and serial-parallel data transform circuit

1997-03-11

1998-08-18

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365219, 365221, 36523003, G11C 700

Patent

active

057966605

ABSTRACT:
In DRAM, a part of data in a row are rewritten at high speed. The memory device comprises dynamic type cell blocks 11; sense amplifiers 3 for sensing data of the cell blocks 11; latches 2 for storing data; data transfer gates for transferring data between the sense amplifiers 3 and the latches 2; and byte write mask circuit blocks 1 for controlling only the data transfer gates corresponding to only the latches 2 in which data have been written, to transfer data to the sense amplifiers 3. The byte write mask circuit block 1 opens only the transfer gates corresponding to the latches 2 to which data are written and further transfer data from the latches 2 to the sense amplifiers 3. Therefore, when data are required to be written in the cell blocks 11, since only the necessary data are written in the latches 2, it is possible to eliminate wasteful data write to the latches 2, thus enabling a high speed data transfer to the cell blocks 11.

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patent: 5361236 (1994-11-01), Iwakiri

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