Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-10-18
2004-03-30
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189070
Reexamination Certificate
active
06714465
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device and process, and more particularly, to a memory device and process for improving the state of one or more terminations in response to process, voltage, and/or temperature variations.
2. Description of the Related Art
A memory device may be connected to an external system, such as a memory controller, through a channel. Signals input from the external system to the memory device through the channel may contain noise, which is caused by a reflected wave. The noise may corrupt the input signal due to the impedance mismatching of the channel. A resistance may be connected to a termination of the memory, to which the input signal is applied, to reduce the noise of the input signal by reducing the reflected wave, thereby improving the state of the termination in the memory device.
For a conventional memory device operated at low speed, the resistance of the termination may be adjusted with a fuse to improve the state of the termination in the memory device and correct process variations. However, the conventional memory device does not vary the resistance value of the termination in the memory device according to variations in voltage or temperature, thereby deteriorating the input/output characteristics of a conventional memory device operated at a high speed.
SUMMARY OF THE INVENTION
In exemplary embodiments, the present invention provides a memory device and process for improving the state of terminations by varying a resistance value connected to the terminations, according to process, voltage, and/or temperature variations.
In an exemplary embodiment of the present invention, a delay locked-loop circuit (DLL) is included in the memory device. The memory device, in an exemplary embodiment, also includes at least one termination, to each of which a variable resistance circuit is connected and through which at least one external signal is passed for operating the memory device and a control circuit for generating a control signal for controlling a resistance value of each of the variable resistance circuits, in response to a command enable signal that represents the activation of an another operation, such as an auto refresh operation, and an external enable signal that activates the DLL in the memory device. After the state of the terminations is improved by the control signal, the DLL is enabled. While the memory device periodically performs the other operation (for example, the auto refresh operation), the state of the terminations is improved by the control signal.
In another exemplary embodiment, the control circuit may include a comparison circuit for generating a control signal by comparing a resistance value of one or more of the variable resistance circuits with an external reference resistance value that is a reference for improving the state of the at least one terminations, and for generating a completion signal after the comparison; a latch circuit for latching the control signal so as to generate a latched control signal in response to an update signal; and a calibration circuit for generating a first internal enable signal to enable the comparison circuit in response to the external enable signal and the command enable signal, for generating the update signal after receiving the completion signal, and for generating a second internal enable signal to activate the DLL after generating the control signal.
In another exemplary embodiment, if a calibration time required for improving the state of the at least one terminations by the control signal is less than a refresh time for the auto refresh operation, the state of the terminations is improved within the refresh time. In another exemplary embodiment, if the calibration time is longer than the refresh time, the comparison circuit is enabled while performing a first auto refresh operation of the auto refresh operation, thereby improving the state of the terminations while performing a second automatic refresh operation performed after the first automatic refresh operation.
In another exemplary embodiment, any or all of the variable resistance circuits may include a first variable resistance connected to an external source voltage, where the first variable resistance may be modified to approach or match an external reference resistance value in response to the control signal; and a second variable resistance connected to a ground voltage, where the second variable resistance may also be modified to approach or match the external reference resistance value in response to the control signal.
In another exemplary embodiment, the present invention is directed to a process for improving the state of at least one termination in a memory device comprising generating a control signal for controlling at least one resistance value of at least one variable resistance circuit, in response to a command enable signal that represents the activation of another operation, such as an auto refresh operation, and an external enable signal that activates a delay locked-loop circuit (DLL) in the memory device; and improving the state of the at least one termination in the memory device based on the control signal; wherein the DLL is enabled after the state of the at least one termination is improved by the control signal, and the state of the at least one termination is improved by the control signal while the memory device periodically performs the another operation (for example, the auto refresh operation).
In another exemplary embodiment, generating the control signal includes comparing the at least one resistance value of the at least one variable resistance circuit with an external reference resistance value that is a reference for improving the state of the at least one termination, generating a completion signal after comparing, latching the control signal to generate a latched control signal in response to an update signal and generating a first internal enable signal to enable the comparison circuit in response to the external enable signal and the command enable signal, generating the update signal after receiving the completion signal, and generating a second internal enable signal to activate the DLL after generating the control signal.
In another exemplary embodiment, if a calibration time required for improving the state of the at least one termination by the control signal is less than a refresh time for the auto refresh operation, the state of the at least one termination is improved within the refresh time, and if the calibration time is longer than the refresh time, the comparison is enabled while performing a first auto refresh operation of the auto refresh operation, thereby improving the state of the at least one termination while performing a second auto refresh operation performed after the first auto refresh operation.
In another exemplary embodiment, the at least one variable resistance circuit includes at least two variable resistances, and the improving includes modifying a value of the first variable resistance, connected to an external source voltage, to approach or match an external reference resistance value in response to the control signal; and modifying a second variable resistance, connected to a ground voltage, to approach or match the external reference resistance value in response to the control signal.
In other exemplary embodiments, the state of the at least one termination is optimized by the control signal while the memory device periodically performs the another operation.
In another exemplary embodiment, the memory device and process according to the present invention receives external signals after improving the state of the terminations according to process, voltage, and/or temperature variations, thereby improving input/output characteristics of the memory device. In other exemplary embodiments, the state of the terminations is improved by an existing command, thereby improving the performance of the memory device. Additionally, the memory device and process according to one or more exemplary
Harness & Dickey & Pierce P.L.C.
Le Thong Q.
Samsung Electronics Co,. Ltd.
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