Memory device and method of simultaneous fabrication of core...

Details Memory device and method of simultaneous fabrication of core... Memory device and method of simultaneous fabrication of core...

2006-06-13

2006-06-13

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S202000

Reexamination Certificate

active

07060564

ABSTRACT:
A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.

REFERENCES:
patent: 5658813 (1997-08-01), Enomoto
patent: 6159795 (2000-12-01), Higashitani et al.
patent: 6248629 (2001-06-01), Liu et al.
patent: 6306706 (2001-10-01), Chan et al.
patent: 6436778 (2002-08-01), Fang et al.
patent: 6509232 (2003-01-01), Kim et al.
patent: 6855608 (2005-02-01), Ramsbey et al.

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