Memory device and method of operating such

Details Memory device and method of operating such Memory device and method of operating such

2007-04-16

2009-12-15

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100, C365S233110

Reexamination Certificate

active

07633814

ABSTRACT:
A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

REFERENCES:
patent: 5835936 (1998-11-01), Tomioka et al.
patent: 6125078 (2000-09-01), Ooishi et al.
patent: 6324096 (2001-11-01), Tomita
patent: 6366529 (2002-04-01), Williams et al.
patent: 7102949 (2006-09-01), Fujioka et al.
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79D, (Revision of JESD79C), JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, Jan. 2004, p. 1 and 5.
128/144-Mbit RDRAM Datasheet (32 Split Bank Architecture), Preliminary Information Version 1.11, Rambus Inc., 2465 Latham Street, Mountain View, California, USA, 94040, 2000, p. 1 and 4.

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