Memory device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S315000, C257S393000, C257SE27013, C257SE27066

Reexamination Certificate

active

07317223

ABSTRACT:
In one embodiment, a memory device includes a semiconductor substrate, a first region formed in a predetermined region of the semiconductor substrate, and in which a plurality of memory transistors are disposed, and a second region adjacent to the first region, and in which a selection transistor is formed to supply a predetermined voltage to the memory transistor. The second region of the substrate may have a higher impurity concentration than an entire region of the substrate other than the second region. Reduced area of the selection transistor can be realized with a shortened channel length, without a decreased threshold voltage.

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patent: 6545310 (2003-04-01), Li et al.
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patent: 6862223 (2005-03-01), Lee et al.
patent: 2004/0140485 (2004-07-01), Matsuzaki et al.
patent: 2005/0047213 (2005-03-01), Umezawa
patent: 2005/0052918 (2005-03-01), Dormans et al.
patent: 2001-210808 (2001-08-01), None
patent: 2003-204000 (2003-07-01), None
patent: 1992-0015541 (1992-08-01), None
English language abstract of Japanese Publication No. 2001-210808.
English language abstract of Japanese Publication No. 2003-204000.
Standards Committee of the IEEE electron Devices Society “IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays” IEEE std 1005-1998, 129 pages.
English language abstract of Korean Publication No. 1992-0015541.

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