Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-03-21
2003-02-04
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S189030, C365S220000, C365S221000, C365S189120
Reexamination Certificate
active
06515914
ABSTRACT:
TECHNICAL FIELD
This invention relates to memory devices, and more particularly to a memory device data path and method that can operate in either a high-speed, narrow data bus mode or a low-speed, wide data bus mode.
BACKGROUND OF THE INVENTION
Memory devices, such as dynamic random access memories (“DRAMs”), have a variety of performance parameters. One of the most important of these performance parameters is the speed at which memory devices are able to read and write data. Generally, memory devices capable of reading and writing data at a higher speed, known as high performance memory devices, are more expensive. Conversely, memory devices that are only capable of accessing data at a slower rate, known as low performance memory devices, must be sold at a cheaper price. In an attempt to increase the operating speed of memory devices, double data (“DDR”) rate DRAMs have been developed. DDR DRAMs are synchronous DRAMs that perform two memory operations each clock cycle—one on each transition of each clock pulse. In a typical DDR DRAM, the memory cells in two adjacent columns having the same column address are read each clock cycle.
Another performance parameter applicable to memory devices is the width of the memory device's data bus. Wider data buses operating at a given speed have a higher bandwidth, i.e., a greater number of bits/second can be accessed. The data bus of most memory devices, such as DRAMs, generally have a width of various powers of 2, i.e., 4, 8, 16, etc. bits.
The need to provide memory devices having different performance parameters generally requires memory device manufacturers to design and manufacture a wide variety of memory devices. For example, memory device manufacturers must design and fabricate relatively expensive memory devices that are capable of operating at a high-speed and different, relatively inexpensive memory devices that are only capable of operating at a relatively low-speed. Unfortunately, it is expensive to design each memory device and the processing needed to fabricate the memory device. The expense of designing and fabricating a variety of different memory devices having different performance parameters is exacerbated by the rapid obsolescence of memory devices as newer devices are introduced at an ever faster rate.
There is therefore a need for memory devices, such as DRAMs, that are capable of operating as either high-speed, narrow data bus memory devices or a low-speed, wide data bus memory devices.
SUMMARY OF THE INVENTION
Data are coupled from a memory array to data bus terminals by transferring 2N bits of parallel data from the array in a first mode and N bits of parallel data in a second mode. The parallel data are transferred from the array to parallel-to-serial converters using a bus having a width of N bits. The parallel-to-serial converters convert the parallel data bits to respective bursts of serial data containing N/M bits and apply the bursts to 2M data bus terminals in the first mode and M data bus terminals in the second mode. The data may be transferred from the memory array in the first operating mode by transferring first and second sets of N data bits from the array in respective first and second read operations. Alternatively, 2N data bits may be transferred from the memory array in a single read operation. As a result, data may be transferred to M data bus terminals at a relatively high-speed in a high performance mode, or to 2M data bus terminals at a relatively low-speed in a low performance mode.
REFERENCES:
patent: 5999458 (1999-12-01), Nishimura et al.
patent: 6084823 (2000-07-01), Suzuki et al.
patent: 6172938 (2001-01-01), Suzuki et al.
patent: 6185149 (2001-02-01), Fujioka et al.
patent: 6252804 (2001-06-01), Tomita
patent: 6400617 (2002-06-01), Aikawa et al.
Johnson Brian
Keeth Brent
Manning Troy A.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Viet Q.
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