Memory device and fabrication method thereof

Details Memory device and fabrication method thereof Memory device and fabrication method thereof

2005-06-14

2005-06-14

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S286000

Reexamination Certificate

active

06905930

ABSTRACT:
The present invention relates to a memory device and the fabrication method thereof. A plurality of pairs of floating gates and a plurality of pairs of select gates are formed above each active region. After forming a dielectric layer on each floating gate and on each select gate, a plurality of pairs of word lines and a plurality of pairs of source lines are formed simultaneously. The word lines and the source lines are disposed in a direction vertical to the strip active regions. A plurality of source/drain regions is disposed in the substrate beside the word lines and the source lines. After forming a thick dielectric layer over the substrate, a plurality of source line contacts are formed in the thick dielectric layer for connecting the source/drain regions that are between each pair of source lines and at least connecting one of each pair of the source lines.

REFERENCES:
patent: 6197639 (2001-03-01), Lee et al.
patent: 6271087 (2001-08-01), Kinoshita et al.
patent: 6624024 (2003-09-01), Prall et al.
patent: 6797570 (2004-09-01), Shin et al.

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