Memory device and fabrication method thereof

Details Memory device and fabrication method thereof Memory device and fabrication method thereof

2005-03-15

2005-03-15

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000, C257S406000, C257S410000, C257S635000, C257S637000, C438S287000, C438S591000

Reexamination Certificate

active

06867453

ABSTRACT:
A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

REFERENCES:
patent: 5424569 (1995-06-01), Prall
patent: 5514889 (1996-05-01), Cho et al.
patent: 6380032 (2002-04-01), Lee et al.
patent: 6614070 (2003-09-01), Hirose et al.

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