Memory device

Details Memory device Memory device

2005-09-20

2005-09-20

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189060, C365S189070

Reexamination Certificate

active

06947338

ABSTRACT:
A memory device is provided, which includes a data receive gate to buffer, in a first buffer, data to be inputted, a data transfer gate to input the data of the first buffer and buffer the same data in a second buffer, a data write gate to output the data of the second buffer to a data bus, and a memory cell to write and store the data in the data bus. In a control circuit thereof, data is not inputted to the first buffer by controlling the data receive gate and at the same time data is inputted to the second buffer by controlling the data transfer gate, depending on a time period from activation of a write enable signal to changing of a data mask signal.

REFERENCES:
patent: 2004/0199717 (2004-10-01), Kanda et al.
patent: 11007770 (1999-01-01), None
patent: 2001351377 (2001-12-01), None
patent: 2003007060 (2003-01-01), None

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