Memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Patent

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Details

365230, G11C 1140

Patent

active

043897142

ABSTRACT:
An memory device having a stable write function and operable with low power consumption is disclosed. The memory device comprises a plurality of digit live pairs, a plurality of memory cells, a bus line, selection means for operatively and selectively transferring a logic level of one digit line of one digit line pair to the bus line and a plurality of digit drive circuits, each of the digit drive circuits being responsive to a first logic level of one digit line of the associated digit line pair for operatively driving a potential of the other digit line of the same digit line pair to a second logic level opposite to the first logic level.

REFERENCES:
patent: 4031552 (1977-06-01), Reed et al.

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