Memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Patent

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Details

365235, G11C 1300

Patent

active

044221606

ABSTRACT:
An improved memory device operable at a high speed and with a small power consumption is disclosed. The memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting columns, a shift register arranged in parallel with the column decoder, first control means for operatively enabling the shift register and second control means for suppressing the operation of the column decoder when the shift register is enabled.

REFERENCES:
patent: 4326270 (1982-04-01), Owens et al.

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