Memory controller for controlling an integrated memory...

Details Memory controller for controlling an integrated memory... Memory controller for controlling an integrated memory...

1999-10-29

2004-01-13

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S323000, C713S502000, C713S601000, C711S167000, C327S141000, C365S233100

Reexamination Certificate

active

06678832

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a memory controller for saving power consumption by stopping clock signal in idling state of system LSI while preventing breakage of memory integrated in the system LSI.
PRIOR ART
In a logic LSI and a microcomputer, in order to save power consumption, it has been often proposed to stop clock signal while idling. The memory used in the logic LSI was mainly the SRAM which can be easily used together with other semiconductors. Basically, the SRAM is composed of flip-flops, and there was no problem if the clock signal is stopped while the LSI is idling.
Recently, owing to the progress in the semiconductor process technology, memories manufactured in different semiconductor processes such as a DRAM and a flash memory can be commonly integrated in one LSI. Since the integrated DRAM does not have a protective circuit for the integrated memory due to the scale limitation of the LSI, it is necessary to operate according to the procedure determined for controlling the DRAM. Therefore, in the system LSI incorporating the DRAM, stopping of clock signal for saving power requires a different method from the logic LSI or microcomputer having the SRAM.
FIG. 4
shows an example of clock signal stop control method in a signal processing circuit and a control signal generating circuit for controlling the signal processing circuit in a conventional video appliance. The conventional clock signal stop controlling method is explained below while referring to
FIG. 4. A
signal processing circuit
101
, when receiving a horizontal synchronization signal
1
, performs various signal processings on the basis of the horizontal synchronization signal
1
. A control signal generating circuit
102
, when receiving the horizontal synchronization signal
1
, generates various control signals, including the control signal for the signal processing circuit
101
on the basis of the horizontal synchronization signal
1
.
Inside of these two circuits, there is a clock signal control unit for stopping and restarting clock signal supply for signal processing and control signal generation. These circuits are composed of logic LSI and SRAM. In thus constituted conventional video appliance, the operation of clock signal stop control method of the signal processing circuit
101
and control signal generating circuit
102
is explained below.
The signal processing circuit
101
and control signal generating circuit
102
operate on the basis of the horizontal synchronization signal
1
. Herein, when the signal processing circuit
101
and control signal generating circuit
102
receive a clock signal suspend command from a clock signal supply control signal
2
not synchronized with the horizontal synchronization signal
1
, immediately responding to the command, the signal processing circuit
101
causes its clock signal control unit to stop the clock signal. Similarly, the control signal generating circuit
102
also stops its internal clock signal.
When the clock signal stops, the signal processing circuit
101
and control signal generating circuit
102
suspend their operation temporarily, and when a clock signal restart command is given by the clock signal supply control signal
2
, the clock signal supply is restarted immediately responding to the command, and the operation is started again. Thus, by simply stopping the clock signal, the signal processing circuit
101
and control signal generating circuit
102
are set in idling state, and the power consumption is saved.
In the conventional clock signal stop control method, since the signal processing circuit and control signal generating circuit are composed of SRAM and logic circuit, no problem was caused even if the clock signal supply was stopped or restarted according to the clock signal supply control signal not synchronized with the horizontal synchronization signal.
However, in the case of LSI with an integrated memory having a logical state such as DRAM, when an asynchronous clock signal supply control signal ignoring the logical state of the memory is put into the LSI and the clock signal supply is stopped according to such signal, the memory cell may be broken down.
SUMMARY OF THE INVENTION
The clock signal stop controller of the invention, in case that a memory having a logical state is integrated in the LSI or the like used in video appliance, is characterized by stopping and restarting clock signal supply without breaking down the memory cell in the following procedure.
1) Receiving a clock signal supply control signal not synchronized with a horizontal synchronization signal which is used as the reference signal, a clock signal supply control signal synchronized with the horizontal synchronization signal is generated.
2) Corresponding to the synchronized clock signal supply control signal, the clock signal is stopped only in the idling state of the logical state of the integrated memory.
3) After restarting the clock signal supply according to the synchronized clock signal supply control signal, the integrated memory is initialized.
The memory controller of the invention has the following constituent elements for the purpose of controlling the clock signal supply to the memory.
a) An operation command generating circuit for generating an operation command for controlling the integrated memory on the basis of the input horizontal synchronization signal.
b) A control signal generating circuit for generating various control signals synchronized with the horizontal synchronization signal by receiving a clock signal supply control signal not synchronized with the horizontal synchronization signal.
c) A power-on sequence command generating circuit for generating a power-on sequence command according to a control signal from the control signal generating circuit.
d) A command selector for selecting either the output signal from the operation command generating circuit or the output signal from the power-on sequence command generating circuit, depending on the output signal from the control signal generating circuit, and outputting the selected signal to the integrated memory.
e) A clock signal cutoff circuit for cutting off the clock signal supplied from the clock signal generating circuit into the integrated memory according to the control signal from the control signal generating circuit.
In this constitution, the invention has the following features.
In the system LSI with an integrated memory, even if a clock signal suspend command signal is input by a clock signal supply control signal not synchronized with the horizontal synchronization signal, the clock signal supply is stopped always in the idling state of the integrated memory. Therefore, the invention can save power consumption by the clock signal stop function in the system LSI without breaking down the integrated memory.


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Yamazaki et al, “A Fully Synchronous Circuit Design for Embedded DRAM”.

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