Memory controller controlling cached DRAM

Details Memory controller controlling cached DRAM Memory controller controlling cached DRAM

2005-08-09

2005-08-09

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S049130, C365S230030

Reexamination Certificate

active

06928003

ABSTRACT:
According to the semiconductor device and method of the present invention, because regular cache memories subjected to hit checks are distinguished from spare cache memories not subjected to hit checks, and because sense amplifiers are also used as cache memories, built-in cache memories are operated faster and at low power consumption. A memory control unit is capable of distinguishing regular memories subjected to hit checks and spare memories not subjected to hit checks. This way, if a hit check is a miss, one of the cache memories not subjected to a hit checks is subjected to a subsequent hit operation and another one of the cache memories not subjected to hit checks is not subjected to the next hit check operation.

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