Memory controller architecture

Details Memory controller architecture Memory controller architecture

1998-02-18

2000-09-12

Dinh, Son T.

Static information storage and retrieval

Addressing

Multiple port access

36518902, 365221, 36523002, G11C 800

Patent

active

061187240

ABSTRACT:
An apparatus for providing a number of ports with burst access to a DRAM array includes a memory array, a controller for controlling the memory array, a write device for writing to the memory array, a read device for reading from the memory array, a FIFO output buffer for temporarily storing data read from the memory array and/or a FIFO input buffer for temporarily storing data prior to writing to the memory array.

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