Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2002-03-19
2003-09-23
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S203000, C711S205000, C711S207000, C711S208000, C711S209000
Reexamination Certificate
active
06625713
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile memory including a logical/physical address control table used for controlling the non-volatile memory in which data is recorded discretely. The memory is composed of a plurality of blocks, each block serving as a data deletion unit and comprising adjacent pages each of which has a fixed length and serves as a data read/write unit. The invention relates to a recording apparatus as well as to a recording method for generating control data cataloged in the logical/physical address control table and used in the non-volatile memory.
BACKGROUND OF THE INVENTION
In recent years, there has been developed a compact storage device that includes solid-state storage, such as a flash memory, and that is mounted on various kinds of equipment, such as a video camera, to store video, audio and computer data.
Since such a storage device is more compact than the other storage mediums, such as a 3.5-inch floppy disc, and employs a drive with a small size, the device can be readily mounted on equipment such as a video camera, an audio recording apparatus and a portable computer apparatus.
Incidentally, a flash memory has the characteristic that the length of its life is affected by the number of repeated writing and erasing operations. With regard to a file system for writing and reading data to and from a storage device utilizing a flash memory like the one described above, the concept of having logical addresses and physical addresses has been introduced. In a configuration employing this concept, operations to write and read out data into and from the storage device are carried out by utilizing the logical and physical addresses.
In order to access the storage device implemented by a flash memory, it is necessary to provide a table showing the relationship between the logical addresses and the physical addresses. Such a table is referred to hereafter as the logical/physical address control table.
In the conventional system, a logical/physical address control table is provided in the main unit utilizing the storage device.
It is noted that, a large logical/physical address control table has a typical data size of about 18 KB depending on the device. On the other hand, the storage capacity of RAM (Random Access Memory) embedded in a 1-chip microprocessor employed in the main apparatus is only several tens of KB at the most. Thus, if the logical/physical address control table is included in the RAM, most of the storage area of the RAM will be occupied by the logical/physical address control table. Therefore, it is quite difficult to store the logical/physical address control table in the RAM embedded in the microprocessor without sacrificing processing performance of the microprocessor. In addition, a low-cost microprocessor may have a RAM capacity of only about 10 KB. In this case, it is impossible to store the logical/physical address control table in the RAM because the size of the logical/physical address control table is larger than the RAM capacity.
To solve the problems described above, the main unit with the storage device formed of a flash memory is provided with an external RAM to store the logical/physical address control table.
An external RAM, however, causes the problems of increased cost, as well as increased power consumption due to the additional power required to drive the external RAM. In particular, if the main apparatus is a portable, battery-powered unit, the increased power consumption adversely affects the life of the battery.
In addition, information recorded in the logical/physical address control table stored in the external RAM is cleared when the storage device is removed from the main unit, and information is recorded in the logical/physical address control table each time the storage device is inserted in the main unit.
In generating of a logical/physical address control table, the microprocessor of the main unit checks the internal state of the storage device and constructs the information in the logical/physical address control table as part of a file-management system. Then, the logical/physical address control table is stored in the external RAM.
It takes at least several seconds to carry out such preparatory processing. In the case of a low-cost microprocessor with a small processing ability, this time increases significantly. For example, since access to write or read out data to or from the storage device can be made only after the preparatory processing is completed, this time appears to the user as an annoying waiting time. If use of the equipment in a way the user likes is taken into consideration, the time it takes to carry out such preparation processing needs to be shortened as much as possible.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a non-volatile memory including a logical/physical address control table and a recording method and apparatus for generating instruction data cataloged in the logical/physical address control table to access the non-volatile memory, whereby the non-volatile memory permits the use of a microprocessor having only a small work memory to access the non-volatile memory.
According to a first aspect of the present invention, there is provided a non-volatile memory that allows a microprocessor having only a small work memory, wherein a storage area of the non-volatile memory comprises an operand data area formed of the blocks making up a plurality of adjacent pages, each page used for recording an identifier for distinguishing operand data from control data and for recording main data. The storage area further comprises an instruction data area formed of the blocks making up the plurality of adjacent pages, each page used for recording an identifier for distinguishing operand data and instruction data from each other and for recording control data representing relations associating logical addresses with physical addresses wherein the logical addresses, are assigned to the data written into the blocks and the physical addresses respect a physical layout of the blocks.
According to a second aspect of the present invention, a recording apparatus generates control data cataloged in the logical/physical address control table and used in accessing the non-volatile memory includes: an attribute determining unit for determining whether data to be written into non-volatile memory is operand data or instruction data; a generating means for generating an identifier indicating whether the data to be written into the non-volatile memory is operand data or instruction data in accordance with a result of determination output by the attribute determining unit; and a memory controller for synthesizing the data to be written into the nonvolatile memory and the identifier output by the identifier and for writing synthesized data into the non-volatile memory.
According to a third aspect of the present invention, a recording method generates control data cataloged in the logical/physical address control table for accessing the non-volatile memory includes the steps of: determining whether data to be written into the non-volatile memory is operand data or instruction data; generating an identifier indicating whether the data to be written into the non-volatile memory is operand data or instruction data in accordance with a result of the determining step; and synthesizing the data to be written into the nonvolatile memory and the identifier output of the generating step and writing synthesized data into the non-volatile memory.
REFERENCES:
patent: 4373179 (1983-02-01), Katsumata
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patent: 5937193 (1999-08-01), Evoy
patent: 6377500 (2002-04-01), Fujimoto et al.
Iida Kenichi
Koga Noriyuki
Obayashi Shuji
Sugiura Mari
Yamada Eiichi
Maioli Jay H.
Peikari B. James
Sony Corporation
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