Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-05-16
2006-05-16
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S105000, C711S170000, C345S570000
Reexamination Certificate
active
07047373
ABSTRACT:
In a memory control apparatus and a method for controlling memory access capable of selecting a desirable page mode, so as to reduce memory access time, a storage circuit receives threshold page hit ratios for each of a plurality of bus masters, and stores the threshold page hit ratios. A page hit ratio computing circuit receives the number of memory accesses by each of the bus masters and the number of page hits by each of the bus masters, computes page hit ratios by each of the bus masters, and outputs the page hit ratios. A comparing circuit compares the threshold page hit ratios with the computed page hit ratios obtained from the page hit ratio computing circuit, and outputs predetermined page mode control signals. The page mode control signals control the page modes of the memory by each of the bus masters in response to the comparison result.
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Peugh Brian R
Samsung Electronics Co,. Ltd.
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