Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-01-22
2002-06-11
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06404668
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a memory configuration which is formed of a plurality of resistive ferroelectric memory cells. Each of the memory cells is formed of a selection transistor and a storage capacitor. One electrode of the storage capacitor is connected to a fixed cell plate voltage and the other electrode of the storage capacitor is connected to a zone of the storage capacitor that has a first conductivity type. The selection transistor and the storage capacitor are provided in or on a semiconductor substrate of a second conductivity type opposite the first conductivity type.
Ferroelectric memory configurations in which the cell plate voltage is permanently set to half the supply voltage (Vcc/2) of the memory configuration are characterized by rapid memory operations. However, in these memory configurations, there is the problem of a possible loss of the data stored in the storage capacitors. Because the cell nodes at the storage capacitors are floating as long as the selection transistors are switched off and these cell nodes form parasitic pn-junctions to the semiconductor substrate, unavoidable leakage currents via the pn-junctions cause the cell node voltage to drop to a ground voltage Vss. The other nodes of the ferroelectric storage capacitors remain here at the fixed cell plate voltage Vcc/2. As a result, the contents of the ferroelectric storage capacitors can be corrupted by reprogramming.
In order to avoid this data loss, in a way similar to DRAMs (Dynamic Random Access Memory Cells), the memory cells are refreshed before their contents are destroyed. The refresh is carried out by the bit lines of the memory configuration being precharged to half the supply voltage Vcc/2, and the cell nodes being also charged to half the supply voltage Vcc/2 by activating the word lines, with the result that 0 V drops across the storage capacitors.
Such a refresh is complicated and requires additional operations which should be avoided if possible.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory configuration having a plurality of resistive ferroelectric memory cells which overcomes the above-mentioned disadvantages of the heretofore-known memory configurations of this general type and which is configured in such a way that a leakage current at the cell node can no longer cause a reprogramming of the memory cell, with the result that a refresh of the memory cell can be dispensed with.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory configuration, including:
a plurality of resistive ferroelectric memory cells, each of the resistive ferroelectric memory cells including a selection transistor and a storage capacitor;
the selection transistor having a given zone of a first conductivity type;
the storage capacitor having a first electrode and a second electrode, the first electrode being supplied with a fixed cell plate voltage, the second electrode being connected to the given zone of the first conductivity type;
a semiconductor body of a second conductivity type opposite the first conductivity type;
the selection transistor and the storage capacitor respectively being provided in or on the semiconductor body;
a resistor;
a line formed by a highly doped zone of the first conductivity type, the line being supplied with the cell plate voltage; and
the second electrode of the storage capacitor being connected via the resistor to the line.
In other words, the object of the invention is achieved in a memory configuration composed of a plurality of resistive ferroelectric memory cells of the type mentioned above in that the other electrode of the storage capacitor is connected via a resistor to a line which is supplied with the cell plate voltage.
According to another feature of the invention, the resistor has a first resistance value. The given zone of the first conductivity type and the semiconductor body form a pn-junction therebetween, and the pn-junction has a reverse resistance with a second resistance value substantially larger than the first resistance value.
According to yet another feature of the invention, the resistor has a given resistance value, the given resistance value is set such that memory read operations and memory write operations, in particular read operations from the resistive ferroelectric memory cells and write operations to the resistive ferroelectric memory cells, are substantially uninfluenced by the resistor.
The resistor in this case is constructed in such a way that its resistance value is substantially lower than the resistance value of the reverse resistance or blocking resistance of the pn-junction between the first zone of the selection transistor and the semiconductor substrate, and in such a way that the read and write operation is influenced by this resistor only to an extremely small degree.
This ensures that in the memory configuration according to the invention the resistance causes virtually no disruption to the read and write operation and nevertheless the leakage current of the parasitic pn-junction to the semiconductor substrate is compensated by this resistance and the voltage present on each side of the ferroelectric storage capacitor is approximately the cell plate voltage. Undesired reprogramming of the storage capacitor can thus no longer occur.
The significant feature of the invention is therefore that the end of the resistor which faces away from the first zone of the selection transistor is connected to the line supplied with the cell plate voltage. This line can preferably be a highly doped zone of the first conductivity type in the surface region of the semiconductor element.
There are various possible ways of implementing the resistor: It is, for example, expedient to provide the resistor through the use of a suitable doping underneath the insulating layer, the so-called thick oxide, in the semiconductor element in the region between the first zone of the selection transistor and the line which is preferably formed from a highly doped zone of the first conductivity type and is supplied with the cell plate voltage. Therfore, according, a preferred feature of the invention, the resistor is a doped layer provided in the semiconductor body; and an insulating layer is disposed above the doped layer.
However, it is also possible to use a MOS transistor for the resistor, a reference voltage being applied to the gate of the MOS transistor in such a way that the resistance with the desired properties, for example in the subthreshold current range, is obtained via the channel of the MOS transistor. Thus, according to a preferred feature of the invention, a MOS transistor has a gate to be supplied with an adjustable reference voltage, and the resistor is implemented by the MOS transistor. In particular, the resistor is formed by the channel region of the MOS transistor.
According to a further feature of the invention, the resistance value of the resistor is set by changing the adjustable reference voltage.
In addition to a constant gate voltage at the gate of the MOS transistor, after each read and write operation and when the supply voltage at the memory configuration is switched on and off, this gate voltage can be set to a value such that the individual electrodes of the storage capacitors, the so-called capacitance nodes, in the memory cells are quickly adjusted to the cell plate voltage.
With such a procedure it is advantageous that the capacitance nodes are adjusted to the cell plate voltage immediately after the respective operation. In this process, it is possible to select all the selection transistors, for example when the memory configuration is switched on and off, or else also to select just the selection transistor which is associated with the respective word line and bit line, with the word or bit line decoder using the voltage applied to the gate of the MOS transistor.
In the memory configuration according to the invention, unintended reprogramming occurring as a result of the
Hoffmann Kurt
Kowarik Oskar
Dinh Son T.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
LandOfFree
Memory configuration including a plurality of resistive... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory configuration including a plurality of resistive..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory configuration including a plurality of resistive... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2922377