Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-01-07
1998-01-06
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Testing
371 211, G11C 700
Patent
active
057062358
ABSTRACT:
An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like). In preferred embodiments, the test mode switch includes a set of series-connected pass transistors and a isolation voltage switch, the pass transistors pass test signals (indicative of test data to be written to or read from a selected cell) directly between the I/O pad and the selected cell in the test mode, and no signals pass through the pass transistors between the I/O pad and any memory cell in the normal mode. In the normal mode of such preferred embodiments, data to be written from the I/O pad to a selected cell passes through an input buffer before reaching the cell (or data to be read from a selected cell passes through an output buffer before reaching the I/O pad), and the isolation voltage switch holds a channel terminal of at least one of the pass transistors at a fixed supply voltage thereby preventing at least one of the pass transistors from undesirably switching on during the normal mode.
REFERENCES:
patent: 4825414 (1989-04-01), Kawata
patent: 4956816 (1990-09-01), Atsumi et al.
patent: 5400281 (1995-03-01), Morigami
patent: 5594694 (1997-01-01), Roohparvar et al.
U.S. Patent Application entitled "Memory System Having Internal State Monitoring Circuit," by Frankie F. Roohparvar, filed Jul. 28, 1995 (Attorney Docket No. MCRN-F1200).
U.S. Patent Application Serial No. 08/386,704 entitled "Apparatus for Entering and Executing Test Mode Operations for Memory", by Frankie F. Roohparvar, filed Feb. 10, 1995.
Briner Michael S.
Roohparvar Fariborz F.
Dinh Son T.
Micron Quantum Devices Inc.
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