Memory circuit with improved serial access circuit arrangement

Details Memory circuit with improved serial access circuit arrangement Memory circuit with improved serial access circuit arrangement

1989-01-27

1991-07-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518912, 365240, G11C 700

Patent

active

050291343

ABSTRACT:
A memory circuit provided with an improved serial access port which can be operated continuously without interruption is disclosed. The memory circuit comprises a plurality of sets of bit lines, each set of bit lines having first and second bit lines, a plurality of sets of latch circuits, eahc set of latch circuits having first and second latch circuits, first means for sequentially deriving data stored in the first latch circuits, second means for sequentially deriving data stored in the second latch circuits, and a plurality of switch circuits, each of the switch circuits being connected between each set of bit lines and each set of latch circuits and selectively providing a signal path between one of the first and second bit lines and one of the first and second latch circuits.

REFERENCES:
patent: 4769789 (1988-09-01), Noguchi et al.

Affiliated with

Also associated with

Rating

Memory circuit with improved serial access circuit arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuit with improved serial access circuit arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit with improved serial access circuit arrangement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1252964