Memory circuit with improved data output control

Details Memory circuit with improved data output control Memory circuit with improved data output control

1988-02-29

1990-01-16

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518911, 3652335, 365203, G11C 700, G11C 1140

Patent

active

048948039

ABSTRACT:
A memory circuit having an improved address change detect circuit which, upon a change of address, forms a first internal one-shot signal for resetting the memory circuit and a second internal one-shot signal for enabling the memory circuit is disclosed. The memory circuit further has a function which, after the read-out data is held by the latch circuit, stops the addressing operation in synchronism with the termination of the second internal one-shot signal, wherein the period for transitting the sense amplifier output to the latch circuit is determined by a period for generating the second internal one-shot signal and, when the first internal one-shot signal is generated, the transmission is preferentially inhibited irrespective of the second internal one-shot signal.

REFERENCES:
patent: 4573147 (1986-02-01), Aoyama et al.
patent: 4592026 (1986-05-01), Matsukawa et al.
patent: 4701889 (1987-10-01), Ando
patent: 4744063 (1988-05-01), Ohtani et al.

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