Memory circuit with high reading speed and low switching noise

Details Memory circuit with high reading speed and low switching noise Memory circuit with high reading speed and low switching noise

2007-12-10

2010-11-02

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189090, C365S189060, C365S189110

Reexamination Certificate

active

07826275

ABSTRACT:
A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.

REFERENCES:
patent: 4992677 (1991-02-01), Isibashi et al.
patent: 5442307 (1995-08-01), Shigehara et al.
patent: 6522596 (2003-02-01), Gillingham et al.
patent: 6906965 (2005-06-01), Cioaca
patent: 7254061 (2007-08-01), Nam et al.
patent: 7391250 (2008-06-01), Chuang
patent: 7447110 (2008-11-01), Chae

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