Memory circuit with foreshortened data output signal

Details Memory circuit with foreshortened data output signal Memory circuit with foreshortened data output signal

1993-02-11

1994-06-28

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365189310, 365203, 365230010, G11C 700

Patent

active

053253302

ABSTRACT:
A memory device output buffer circuit provides an output data signal only when data is valid. According to the present invention, the circuit for a memory read function provides a pair of signals equilibrated prior to each read operation. Data is valid when the signals are complementary. For a tristate output, the complementary condition enables the output buffer. In a semiconductor dynamic random access memory (DRAM) connectable to a bidirectional data bus, the three-state output buffer of the present invention is not enabled during a read operation until data is valid. Spurious output data signals are prevented from consuming power. As an additional benefit, the bus is not dedicated to the memory when valid data is not yet available.

REFERENCES:
patent: 4649522 (1987-03-01), Kirsch
patent: 4849935 (1989-07-01), Miyazawa
patent: 4894803 (1990-01-01), Azaki
patent: 4953130 (1990-08-01), Houston
patent: 5027326 (1991-06-01), Jones
patent: 5088065 (1992-02-01), Hanamura
patent: 5245573 (1993-09-01), Nakaoka

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