Memory circuit having an improved writing scheme

Details Memory circuit having an improved writing scheme Memory circuit having an improved writing scheme

1986-03-18

1988-08-30

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 365191, 365230, G11C 1100, G11C 700, G11C 800

Patent

active

047681683

ABSTRACT:
An improved memory circuit having a fast write speed is disclosed. A first control signal is generated when a first period of time has elapsed from the initiation of an access cycle, in a fixed timing both in a read operation and a write operation. A second control signal for enabling a data input circuit when a second shorter period has elapsed from the initiation of the access cycle only in a write operation. A data transfer between a selected bit line and a bus line is performed when at least one of the first and second control signals.

REFERENCES:
patent: 4272834 (1981-06-01), Noguchi et al.
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4592022 (1986-05-01), Shimohigashi et al.
patent: 4651306 (1987-05-01), Yanagisawa
patent: 4658377 (1987-04-01), McElroy

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