Memory circuit apparatus

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S185250

Reexamination Certificate

active

06950360

ABSTRACT:
A memory circuit device comprising a plurality of memory cells connected to a plurality of bit lines and word lines, an access circuit connected to the plurality of bit lines and word lines to select predetermined memory cells from the plurality of memory cells in response to an address signal, a precharge circuit which precharges the bit lines connected to the memory cells selected by the access circuit at the time of a read mode, a common source line connected to a plurality of selected memory cells selected by the access circuit, a source line potential control circuit to connect the common source line to a ground node at a predetermined timing, and a discharge circuit which discharges the bit lines connected to non-selected memory cells other than the selected memory cells.

REFERENCES:
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patent: 5270978 (1993-12-01), Matsumoto et al.
patent: 5453955 (1995-09-01), Sakui et al.
patent: 5687123 (1997-11-01), Hidaka et al.
patent: 5949727 (1999-09-01), Choi et al.
patent: 6018487 (2000-01-01), Lee et al.
patent: 6058044 (2000-05-01), Sugiura et al.
patent: 6072734 (2000-06-01), Choi
patent: 6195297 (2001-02-01), Sano

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