Memory circuit and method of operation therefor

Static information storage and retrieval – Systems using particular element – Capacitors

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Details

365175, 365203, 36523003, G11C 1124

Patent

active

057176299

ABSTRACT:
A memory array circuit has a matrix of column lines and row lines. A plurality of storage capacitors are arranged in the matrix, with each storage capacitor having a data node and a voltage node. Each of the plurality of storage capacitors has an associated column line and an associated row line, with the voltage node connected to the associated row line. A diode connects the data node of a storage capacitor to its associated column line. A first decoder decodes a first address signal and selects one of the column lines. A second decoder decodes a second address signal, and generates a row output signal, with each row output signal of the second decoder having a corresponding row line. A plurality of voltage control circuits is provided with each voltage control circuit receiving one of the plurality of row output signals, and for applying a control signal to a corresponding row line, in response to a data read signal, a data write to one state signal or a data write to another state signal.

REFERENCES:
patent: 3986173 (1976-10-01), Baitinger et al.
patent: 4247918 (1981-01-01), Iwashashi et al.
patent: 4360897 (1982-11-01), Lehovec
patent: 4573143 (1986-02-01), Matsukawa
patent: 4920513 (1990-04-01), Takeshita et al.
patent: 5483482 (1996-01-01), Yamada et al.
patent: 5535156 (1996-07-01), Levy et al.
patent: 5566371 (1996-10-01), Ogawa
"Pinch Load Resistors Shrink Bipolar Memory Cells" by S.K. Wiedmann, Electronics, Mar. 7, 1974, pp. 130-133.

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