Memory circuit

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Patent

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Details

365227, 307449, G11C 1140

Patent

active

045204632

ABSTRACT:
A memory circuit having an improved address decoder which is operable with a low power consumption and can be fabricated at a high-integration is disclosed.
The memory comprises a logic means for decoding a part of address signals provided for a plurality of address lines of a memory cell array, and a plurality of transfer gates provided between the logic means and the address lines, in which one of those transfer gates is made enabled in response to a different part of the address signals thereby to transmit the output signal of the logic means to a selected row line through the enabled transfer gate.

REFERENCES:
patent: 4422160 (1983-12-01), Watanabe

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