Memory cells with vertical transistor and capacitor and...

Details Memory cells with vertical transistor and capacitor and... Memory cells with vertical transistor and capacitor and...

2008-03-11

2008-03-11

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27092

Reexamination Certificate

active

11145862

ABSTRACT:
Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated from the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

REFERENCES:
patent: 4713678 (1987-12-01), Womack et al.
patent: 5821579 (1998-10-01), Choi et al.
patent: 6750499 (2004-06-01), Wu
patent: 6808979 (2004-10-01), Lin et al.
patent: 2003/0062568 (2003-04-01), Beinter
patent: 2004/0065914 (2004-04-01), Koike et al.
patent: 2005/0285175 (2005-12-01), Cheng et al.

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