Memory cells with improved program/erase windows

Details Memory cells with improved program/erase windows Memory cells with improved program/erase windows

2006-12-05

2009-08-11

Purvis, Sue (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257S335000, C257S314000, C257S315000, C257S321000, C257SE21683, C257SE21691, C438S278000

Reexamination Certificate

active

07573095

ABSTRACT:
A semiconductor structure includes a memory cell in a first region and a logic MOS device in a second region of a semiconductor substrate. The memory cell includes a first gate electrode over the semiconductor substrate; a first gate spacer on a sidewall of the first gate electrode, wherein the first gate spacer comprises a storage on a tunneling layer; and a first lightly-doped source or drain (LDD) region and a first pocket region adjacent to the first gate electrode. The logic MOS device includes a second gate electrode on the semiconductor substrate; a second gate spacer on a sidewall of the second gate electrode; a second LDD region and a second pocket region adjacent the second gate electrode, wherein at least one of the first LDD region and the first pocket region has a higher impurity concentration than a impurity concentration of the respective second LDD region and the second pocket region.

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Fukuda, M., et al., “Scaled 2 bIt/cell SONOS Type Nonvolatile Memory Technology for sub-90nm Embedded Application using SiN Sidewall Trapping Structure,” 2003 IEEE, IEDM 03, pp. 909-912.

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