Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent
1997-10-16
2000-09-19
Cabeca, John W.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
711201, 711100, G06F 1200, G11C 1100
Patent
active
061227021
ABSTRACT:
The invention relates to a matrix of memory cells for a semiconductor integrated microcontroller. The matrix is of the type intended for accommodation between macrocells of the microcontroller so as to reduce the needed circuit area on the semiconductor. The matrix comprises memory cells which are organized into rows and columns, with the number of columns defining the matrix height. The matrix height is advantageously variable according to the number of bits intended for selecting the matrix column, while its width is dependent on the overall capacity of the memory.
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Olivo Marco
Pelagalli Sergio
Bataille Pierre-Michel
Cabeca John W.
Galanthay Theodore E.
SGS--Thomson Microelectronics S.r.l.
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