Memory cell with transistors having relatively high...

Details Memory cell with transistors having relatively high... Memory cell with transistors having relatively high...

2001-12-13

2004-08-10

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S181000, C438S184000, C438S217000, C438S231000, C438S276000, C257S204000, C257S288000, C257S341000, C257S371000

Reexamination Certificate

active

06773972

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The present embodiments relate to transistor circuits and are preferably directed to a memory with storage cells having transistors with relatively high threshold voltages.
The technology of many modern circuit applications continues to advance at a rapid pace. One incredibly prolific type of circuit, and one which is highly developed, is digital memory. For such memories, consideration is given to all aspects of design, including maximizing efficiency and increasing performance. These considerations may be evaluated based on the integrated circuit device in which the memory is formed, where such devices may be implemented either as stand-alone products or as part of a larger circuit such as a microprocessor. One often critical factor with respect to digital memories is the cost of the device and this cost is often affected by the overall size of the memory architecture.
In response to the above considerations, recent interest has grown in the use of a so-called 4T memory cell, where this name suggests that each cell includes a total of four transistors. As detailed later in this document, two of the transistors in the 4T cell provide access to the state of the cell, that is, to either read data from or write data to, the cell. These transistors are referred to in this document as access transistors, although they may be referred to using various other terms in the art. The remaining two transistors in the cell are cross-coupled and maintain the state of the cell once it is written. These two transistors are referred to in this document as state transistors, although they too may be referred to using various other terms in the art. In any event, one of the reasons that the 4T cell has received favor is because it is smaller than other memory cells, such as a standard 6T (i.e., six transistor) memory cell. Additionally, the 4T cell reduces the standby current consumption in large area memory arrays as compared to more complex cell architectures.
While the 4T cell provides various benefits, a key consideration in its operation is that its two access transistors, which typically are p-channel metal oxide semiconductor (PMOS) transistors, must be designed to have a greater leakage current than its two state transistors, which typically are n-channel MOS transistors (i.e., NMOS). In the prior art, the reduced leakage in the state transistors is achieved by increasing the threshold voltage of those state transistors, thereby decreasing their leakage. However, the memory cells, and hence the state transistors, are typically part of a larger memory circuit that includes other NMOS circuits, such as in input/output devices or amplifiers also formed in connection with the memory circuit. Thus, while the threshold voltage of the n-channel state transistors may be increased to achieve desirable operation within a cell, the threshold voltage of other NMOS devices on the memory circuit typically must be left to a lower level so as to preserve the desired circuit operation (e.g., speed, current consumption) of those other NMOS devices. In other words, this prior art approach requires a dual or selective VT process with respect to the NMOS devices, whereby one threshold voltage is established for the NMOS state transistors while another threshold voltage is established for some or all of the other NMOS transistors on the same circuit chip.
To achieve the above-described dual threshold voltage structure, the prior art includes a technique where multiple masks and multiple doping steps are used to create different dopant concentrations in the channel region for the various NMOS transistors of the memory circuit. More particularly, a first mask step followed by a first doping step are used to establish a first dopant concentration in the channel region of a first set of NMOS transistors and thereby to cause those transistors to have a first threshold voltage, and a second mask step followed by a second doping step are used to establish a second dopant concentration in the channel region of a second set of NMOS transistors and thereby to cause those transistors to have a second threshold voltage which is different than the first threshold voltage. However, this approach requires two sets of masks and two implant steps with respect to the channel of the NMOS devices. Thus, it increases the processing complexity and thereby adds costs to the device. As such, these drawbacks negate some of the benefits of using 4T cells in the first place.
In view of the above, there arises a need to address the drawbacks of the prior art as is achieved by the preferred embodiments described below.
BRIEF SUMMARY OF THE INVENTION
In the preferred embodiment, there is a method of forming a semiconductor circuit. The method forms a first transistor using various steps, such as by forming a first source/drain region as a first doped region in a fixed relationship to a semiconductor substrate and forming a second source/drain region as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor using various steps, such as by forming a third source/drain region as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region as a fourth doped region in a fixed relationship to the semiconductor substrate. The fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions. Additionally, the second transistor is formed by forming a second gate in a fixed relationship to the third source/drain region and the fourth drain region. Also in the preferred embodiment method, the steps of forming the first gate and the second gate comprising forming the first gate to comprise a first dopant concentration and forming the second gate to comprise a second dopant concentration different from the first dopant concentration. Other methods, circuits, and systems are also disclosed and claimed.


REFERENCES:
patent: 2002/0137320 (2002-09-01), Nishihara et al.

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