Memory cell structure having a vertically arranged transistors a

Details Memory cell structure having a vertically arranged transistors a Memory cell structure having a vertically arranged transistors a

1995-03-17

1998-10-27

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257300, 257303, 257304, 257306, H01L 27108

Patent

active

058280944

ABSTRACT:
A buried bit line cell and a manufacturing method thereof increases the integration density of a semiconductor device such as a DRAM. The semiconductor device includes: a semiconductor substrate having a plurality of spaced apart first pillars formed therein with isolated first trenches therebetween and second pillars connected to the first pillars thereunder with isolated second trenches therebetween; a first isolation insulating layer formed inside the first trenches and isolated by a gate insulating layer and gate electrode enclosing the first pillars; impurity-doped regions having a first and second impurity-doped region vertically formed in the first and second pillars and a channel region therebetween; a bit line formed in the bottom and on the sidewalls of the second trenches and connected to the impurity-doped regions; a second isolation insulating layer formed in the bottom of the first trenches and inside the second trenches, for isolating the bit lines; and a word line isolated by the first isolation insulating layer and connected to the gate electrode. Problems due to a deep trench and step formation are resolved by controlling the height of the first and second pillars and the storage node of a capacitor.

REFERENCES:
patent: 4937641 (1990-06-01), Sunami et al.
patent: 5504357 (1996-04-01), Kim et al.
IBM, TDB vol. 34 No. 7B, "Method of Fabricating a New Merged Stacked Trench Capacitor Memory Cell", Dec. 1991, pp. 472-476.

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