Memory cell, memory cell configuration and fabrication method

Details Memory cell, memory cell configuration and fabrication method Memory cell, memory cell configuration and fabrication method

2005-01-18

2005-01-18

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S316000, C365S185010, C365S185140

Reexamination Certificate

active

06844584

ABSTRACT:
Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

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