Memory cell leakage detection circuit

Details Memory cell leakage detection circuit Memory cell leakage detection circuit

1985-11-14

1987-08-04

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365200, 365201, G11C 1140

Patent

active

046850864

ABSTRACT:
A circuit for detecting a short circuit in a SRAM memory cell (10) includes means for connecting the nodes (21, 23) of the memory cell to the gates of a pair of pulldown transistors (66, 68). The pulldown transistors perform a level-shifting function to produce a voltage pattern that has one high node and one low node (72, 74) for a normal cell and two intermediate voltage nodes for a shorted cell. A following logic circuit (76) responds to the voltage pattern to produce an output voltage that has one value when the cell is functioning correctly and another value when the cell is shorted.

REFERENCES:
patent: 4386419 (1983-05-01), Yamamoto
patent: 4459686 (1984-07-01), Toyoda
patent: 4502140 (1985-02-01), Proebsting
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4580245 (1986-04-01), Ziegler et al.

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