Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-30
2001-07-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S296000
Reexamination Certificate
active
06262448
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor structures and more particularly to dynamic random access memory structures.
As is known in the art, for the commercial success of future generations of semiconductor memories, it will be essential to minimize die sizes and at the same time increase performance characteristics. One type of semiconductor memory is a dynamic random access memory (DRAM). In one such DRAM, an array of memory cells is provided. Each one of the memory cells incudes a transistor coupled to a storage capacitor. In a deep trench DRAM cell, the capacitor is formed in a deep trench which passes vertically into the surface of the semiconductor thereby reducing size as compare to a stack capacitor cell. Still, as noted above, for commercial success cell sizes must continue to be reduced.
SUMMARY OF THE INVENTION
In accordance with the present invention, a DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body.
With such an arrangement a DRAM cell is provided which occupies a relatively small amount of surface area of the semiconductor body.
In accordance with another embodiment invention, the transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body.
In accordance with another invention, a bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell.
REFERENCES:
patent: 5032882 (1991-07-01), Okumura et al.
patent: 5216266 (1993-06-01), Ozake
patent: 5821579 (1998-10-01), Choi et al.
“Silicon Processing for the VLSI Era, vol. 2: Process Integration” by Stanley Wolf, Ph.D., Lattice Press, California.
Enders Gerhard
Ilg Matthias
Risch Lothar
Widmann Dietrich
Infineon Technologies North America Corp.
Loke Steven
Owens Douglas W.
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