Memory cell having enhanced high-K dielectric

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S314000, C257S324000, C257S325000, C257S390000, C257S391000, C257SE29304, C257SE29309

Reexamination Certificate

active

11008233

ABSTRACT:
A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

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Co-pending U.S. Appl. No. 11/128,392, filed May 13, 2005; entitled: “SONOS Memory Cell Having a Graded High-K Dielectric”, by Takashi Whitney Orimoto et al., 31 pages.
Co-pending U.S. Appl. No. 11/049,855, filed Feb. 4, 2005; entitled: “Non-Volatile Memory Device With Improved Erase Speed”, by Joong Jeon et al., 22 pages.
Co-pending U.S. Appl. No. 11/086,310, filed Mar. 23, 2005; entitled: “High K Stack For Non-Volatile Memory”, by Wei Zheng et al., 21 pages.
Co-pending U.S. Appl. No. 11/196,434, filed Aug. 4, 2005; entitled: “SONOS Memory Cell Having High-K Dielectric”, by Takashi Whitney Orimoto et al., 27 pages.

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