Memory cell having bar-shaped storage node contact plugs and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S300000, C257S306000, C257SE21648, C438S253000

Reexamination Certificate

active

10891806

ABSTRACT:
According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line capping layer pattern stacked thereon. Bit line spacers covers side walls of the bit line patterns, buried holes penetrate predetermined regions of the bit line interlayer insulating layer between the bit line patterns. And a plurality of storage node contact plugs are placed between the bit line patterns surrounding by the bit line spacers. At this time, the storage node contact plugs fill the buried holes.

REFERENCES:
patent: 5879986 (1999-03-01), Sung
patent: 5895239 (1999-04-01), Jeng et al.
patent: 6037216 (2000-03-01), Liu et al.
patent: 6127260 (2000-10-01), Huang
patent: 6136643 (2000-10-01), Jeng et al.
patent: 6150213 (2000-11-01), Luo et al.
patent: 6255160 (2001-07-01), Huang
patent: 2001/0001717 (2001-05-01), Kumauchi et al.
patent: 2002/0079536 (2002-06-01), Terauchi et al.
patent: 1999-003042 (1999-01-01), None
patent: 2000-0015399 (2000-03-01), None
patent: 2002-0002924 (2002-01-01), None
patent: 2003-0002871 (2003-01-01), None
patent: 2003-0059415 (2003-07-01), None
English language abstract of Korean Publication No. 2000-0015399.
English language abstract of Korean Publication No. 2005-0002924.

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