Memory cell circuit with single bit line latch

Details Memory cell circuit with single bit line latch Memory cell circuit with single bit line latch

1993-09-16

1994-10-04

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 365156, G11C 700

Patent

active

053532511

ABSTRACT:
A memory cell circuit for a CMOS static RAM is provided, which includes a latch portion for holding logic high or logic low data depending on the potential of a single bit line, and a transfer gate having a first terminal connected to the latch portion and a second terminal connected to the single bit line, the transfer gate electrically connecting or disconnecting the first and second terminals in response to a selection signal, wherein the transfer gate includes a first transistor and a second transistor connected in parallel between the first and second terminals, both of the first and second transistors being activated at a data write operation, while one of the first and second transistors being activated at a data read operation.

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