Memory cell array structures in NAND flash memory devices

Details Memory cell array structures in NAND flash memory devices Memory cell array structures in NAND flash memory devices

2006-12-28

2008-12-30

Dang, Phuc T (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S318000, C438S247000, C438S258000

Reexamination Certificate

active

07470948

ABSTRACT:
A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns, and the memory gate structure includes a plurality of storage gate patterns. The gate insulating layer includes a plurality of openings therein exposing portions of the active region between ones of the plurality of select gate patterns of the first and second select gate structures. The device may further include impurity regions in portions of the active region between the gate patterns, and halo regions adjacent ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer. Related fabrication methods are also discussed.

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Notice to File a Response/Amendment to the Examination Report corresponding to Korean Patent Application No. 10-2006-0021440 mailed Apr. 24, 2007.
Notice of Allowance corresponding to Korean Patent Application No. 10-2006-0021440 mailed Apr. 8, 2008.

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