Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1998-06-09
1999-09-21
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Bad bit
36518909, 365195, G11C 700
Patent
active
059562757
ABSTRACT:
An array of memory cells are arranged in rows and columns. The array includes a plurality of cell plates that are each coupled to at least one of the memory cells. A generator produces a bias voltage. A plurality of isolation circuits are each coupled between the generator and one or more of the cell plates. Each isolation circuit provides the bias voltage to the cell plate or plates to which the isolation circuit is coupled. The cell plates may be coupled to memory cells from a plurality of the columns. Additionally, each of the isolation circuits may selectively provide, in response to a control signal, the bias voltage to the cell plate or plates to which the isolation circuit is coupled.
REFERENCES:
patent: 5079743 (1992-01-01), Suwa et al.
patent: 5079746 (1992-01-01), Sato
patent: 5235550 (1993-08-01), Zagar
patent: 5301143 (1994-04-01), Ohri et al.
patent: 5373463 (1994-12-01), Jones, Jr.
patent: 5450360 (1995-09-01), Sato
patent: 5469391 (1995-11-01), Haraguchi
patent: 5615144 (1997-03-01), Kimura et al.
Le Vu A.
Micro)n Technology, Inc.
LandOfFree
Memory-cell array and a method for repairing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory-cell array and a method for repairing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory-cell array and a method for repairing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-86585