Static information storage and retrieval – Read/write circuit – Multiplexing
Patent
1989-07-31
1990-11-13
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Multiplexing
365219, G11C 700
Patent
active
049706900
ABSTRACT:
A memory cell and array of memory cells specially adapted for support of bit serial math for low cost CAD workstations. The memory cell is comprised of a multiplexer which selects between several inputs for application of data to a bit storage cell of a dynamic RAM nature. Each cell multiplexer has a serial data input, a parallel data input, a parallel format pipeline data input and a recirculation data input. Each cell also has a first output which serves both as a serial data output and a pipeline data output, and a second data output which is tri-state and which is coupled to a parallel format data bus which runs through the array. A plurality of such cells are arranged in rows and columns where rows of such cells are coupled so that data may passed between the rows in either parallel format or serial format for pipeline operations and such each row can independently load data in either serial or parallel format and output data in either parallel or serial format. Ech cell has a selectable recirculation path which allows any cell or group of cells to be used as RAM or as a shifting network.
REFERENCES:
patent: 4435792 (1984-03-01), Bechtolsheim
patent: 4685088 (1987-08-01), Iannucci
Atari Games Corporation
Fish Ronald C.
Popek Joseph A.
LandOfFree
Memory cell arrangement supporting bit-serial arithmetic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory cell arrangement supporting bit-serial arithmetic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell arrangement supporting bit-serial arithmetic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-781782