Memory cell arrangement of memory cells arranged in the form of

Details Memory cell arrangement of memory cells arranged in the form of Memory cell arrangement of memory cells arranged in the form of

1996-07-16

1998-10-20

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365210, G11C 700

Patent

active

058257012

ABSTRACT:
The memory cell arrangement has MOS transistors (10) connected between bitlines (4, 4.sub.1) and connected row-by-row by means of selection lines (5). For pre-charging of all the bitlines (4, 4.sub.1) without a blocking of an access to these lines, further MOS transistors (20), connected between the bitlines (4, 4.sub.1) and a supply line (7), are provided, whose gate terminals (20.sub.2) are connected to a common pre-charging line (6).

REFERENCES:
patent: 3848236 (1974-11-01), Troutman
patent: 5414663 (1995-05-01), Komarek et al.

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